Decoder Using – Verilog

3 to 8 Decoder using Verilog Programming

Content to be covered :

  • Decoder -> what is it?
  • Truth Table
  • Enable logic
  • Verilog Code
  • RTL view
  • Testbench
  • Stimulation

1. Decoder -> what is it?

A decoder is a digital circuit, that helps convert an given n coded input to a 2n outputs.

A decoder various applications such as data multiplexing and data demultiplexing, seven segment displays, and as address decoders for memory and port-mapped I/O.

There are few different types of decoders. For example, the above is 1-of-n type of binary decoder, meaning that when, an input is given only 1 or none of the output is activated.

A binary decoder is usually implemented as a standalone IC or as a part of more complex ICs.

So, if there are N inputs, the decoder will produce a maximum of 2n outputs. Thus, if we have 3-bit input we will have 23 = 8-bit output. In Verilog Coding, of a particular combinational circuit it is necessary to know the number of input/output a particular chip may require.

Since, we now understand the concept behind the decoder, we should start with the logic oriented part.

2. Truth Table

Any digital circuit can be realized using Truth Table. This is the beauty of digital Electronics. Also using this table to simplify the logic of the design we initially thought off.

DINDOUT
000 00000001
001 00000010
010 00000100
011 00001000
100 00010000
101 00100000
110 01000000
111 10000000
Truth Table for 3 to 8 decoder

3. Enable Logic

Yes, the theoretical part of the design is almost over with the understanding of the enable input, which is the driver of the combinational logic. Take a look at the transformed truth table

EnableDINDOUT
1XXX00000000
000000000001
000100000010
001000000100
001100001000
010000010000
010100100000
011001000000
011110000000
Truth Table for 3 to 8 decoder with enable

You can see that the design modifies in a sense that if the enable is logic 0 => the output becomes zero no matter the input. Thus, this enable can be used as a switch by many devices in order to keep this device “on” only in the time of need. Also, this type of enabling is called active low, since the chip gets activated when the enable turns low(i.e. enable = 0).

4. Verilog Code

Okay so without further delay, here’s the code for decoder.

Also here is the link to my git repo -> https://github.com/nirbhay12345/chipDesign/Decoder

module Decoder ( // 3 to 8 decoder
    input [2:0] din, // input signal
    input enable, // chip enable signal => active low
    output reg [7:0] dout // selected output
);

    // main logic
    always @* begin
        if (enable)
            dout[7:0] <= 8'h00;
        else
            case (din[2:0])
                3'b000 : dout[7:0] <= 8'h01;
                3'b001 : dout[7:0] <= 8'h02;
                3'b010 : dout[7:0] <= 8'h04;
                3'b011 : dout[7:0] <= 8'h08;
                3'b100 : dout[7:0] <= 8'h10;
                3'b101 : dout[7:0] <= 8'h20;
                3'b110 : dout[7:0] <= 8'h40;
                3'b111 : dout[7:0] <= 8'h80;
                //default is necessary to avoid any latchs
                default: dout[7:0] <= 8'h00; 
            endcase
    end

endmodule

5. RTL view

The design thus converted into a simple combinational logic. Also, you can always convert it into a parametric form in order to scale things up. But that’s up to you to decide.

Generated using Xilinx ISE

6. Testbench

Here is the testbench :

module Decoder_tb;
    reg [2:0] din;
    reg enable;
    wire [7:0] dout;

    // instantiate the design block
    Decoder d1(din, enable, dout);

    integer i;

    initial begin
        enable = 1'b1;
        din = 3'b000;
        i = 0;
        #100
        enable = 1'b0;
        for (i = 0; i < 8; i=i+1) begin
            din = din + 3'b001;
            #100;
        end
    end

endmodule

The above testbench probably includes all the possibility of the design and thus completes our design. Just one thing to Go -> Stimulation.

7. Stimulation

Time to test and observe our design.

Great going !! We now have a decoder of our own! 😎

Verilog Programming – full adder

Full adder using Verilog and Isim stimulation.

Concepts covered in the blog :

Half adder

If you are reading this blog, then you are probably familiar with digital electronics. If not then here is some basic on full adder what it is and why we need it, if yes then this might be a quick revision for you all.

So what is a full adder? before that we need to know what is a half adder.

Basically, half adder is a digital circuit which adds two bits. It is the simplest form of a adder circuit.

Let us take that bits to be A and B. Thus what the half adder digital circuit does is that, it generates a Sum and Carry according to the given input.

ABSumCarry
0000
0110
1010
1101
Truth table for a half adder

Thus, from the truth table we can infer the following Boolean equations :

A ⊕ B = Sum

A . B = Carry

Thus, we can easily obtain the above visualization of half adder.

Full adder -> Concept

Half adder is good enough but the tricky part begins when we switch to addition of more than one bit. Yes, you guessed it right.

In addition of more than two bits, we need to consider the Carry that is generated by the LSB (Least Significant Bit), or to say the bit having a lesser place value.

Here, full adder comes into picture. the full adder also takes into consideration the carry of the previous bit, increasing one input in the circuit, this might be more clear by seeing the truth table and then visualizing the full adder.

ABCinSumCout
00000
00110
01010
01101
10010
10101
11001
11111
Truth table for Full Adder

Sum = A ⊕ B ⊕ Cin

Cout = A.B + Cin(A ⊕ B)

Thus, by now you might be clear about what a half adder and full adder does and comprises off.

Now, to answer the question -> how can you create actual hardware, using the HDL language like Verilog?

Verilog Code

Verilog is one of the languages used to describe hardware, hence the name -> HDL (Hardware Description Language).

You might need a tool like -> Xilinx ISE design suite or others to create the following. Better to check you have installed everything.

module adder_carry(
    input wire [3:0] i_a, i_b,
    output wire [3:0] o_sum,
    output wire o_cout
    );

	wire [4:0] int_sum;
	
	assign int_sum = {1'b0, i_a} + {1'b0, i_b};
	assign o_sum = int_sum[3:0];
	assign o_cout = int_sum[4];
	
endmodule

The above code represents a 4-bit full adder Verilog code.

The 5th bit of the int_sum variable is taken to represent the carry generated from MSB of the addition of i_a and i_b signals.

RTL view

The RTL view is generated by the tool you are using automatically, by just synthesizing the code.

It has predefined hardware for a particular code and the tool then converts your written code into actual hardware schematic.

The above given is the RTL view of the code written above. It is necessary to understand that through Verilog we are trying to create a hardware and thus the RTL view helps us to visualize the hardware schematic before it can be further evaluated.

Also, RTL view helps us to see what does the hardware comprises of and gives us a digital circuit insight for further understanding of the hardware.

Different methods in Verilog may give different hardware approaches, thus the choice of hardware customization entirely depends over the designer and the methods he/she may use.

Finally, our goal is to make systems with the most efficient yet with reasonable hardware, where the trade-off between the hardware and the speed of execution of a particular task plays an important role.

Stimulation (ISIM)

The stimulation of a given circuit further helps us to understand the response of the circuit in dynamic conditions. Thus, helping us to know the in’s and out’s of the circuit.

This helps in visualization of the circuit response and also rectifies for any error that our system may possess.

The Stimulation of the above Verilog code is given below.

The result is as expected.

Wish you a happy learning!!